What is an SPI interface

The SPI interface was developed by Motorola. To date, it is one of the most popular, due to its high speed and exceptional simplicity, from all those that belong to the serial type. In addition, the SPI interface is also a communication principle. In fact, the SPI is a data transfer logic (master-slave) between two different devices. Physical properties are given much less attention, they are realized, as they say, "by the circumstances", while there is no protocol for the lower level. Each manufacturer can contribute something of its own.

SPI interface: description

The logic of such a device consists in the serial transmission of data (bitwise). In this case, the installation and reading are separated in time due to a special clock on a special bus (it is called a "clock bus" or "synchronization"). Under the separation is understood that the process of installing and reading data occurs on opposite fronts of the sync pulse generated on the bus. Due to this clearly separated timing of the readings and settings, it is possible to use the same register for receiving and transmitting information. It is under this principle and developed the SPI-interface. However, the development of technology does not stand still, to date, large amounts of memory do not present any problems, and most devices have separate input and output registers. In a nutshell, we looked at how the SPI interface works.

Description of the device operation

The device that generates the clock (control) on the clock bus is the master (master). Such a device manages the entire data exchange process, that is, determines when to start the exchange, when to finish, how many bits of information to transmit, etc. The second device participating in the exchange is called the "slave". This device does not affect the timing bus in any way. For full-duplex communication (transfer in both directions at the same time), the SP interface uses four lines:

- MOSI - master output and slave input. This line transfers information from the main device to the receiving one.

- MISO - the input of the master and the output of the "slave". On this wire, the master receives data from the auxiliary device.

- SCLK - clocking bus. On this line, the "master" device generates sync pulses.

- SS - selection of the "slave". With this wire, the master manages the exchange session.

Levels of logical zero and units are encoded by the voltage value on the data bus (MISO and MOSI). The SS signal indicates the end and start of the communication session. Most often it is inverted. This means that during the data exchange, the "master" device must establish a low level signal on the SS line, and at the end of the exchange a high signal. The presence of the SS level allows for the transmission of several "slaves" using one synchronizing signal and one data bus without additional protocols. True, with this connection it is necessary to provide a separate SS line from each receiver.